Field of the Invention
The invention relates to a method for processing digital signals, such as clock signals, for example. The invention additionally relates to a circuit configuration for carrying out the method.
It is frequently the case that only edges are evaluated during the processing of digital signals. An edge is understood to mean a change from one logic state to another logic state. The change of a signal from a logic zero to a logic one is referred to as a rising edge, and the change from a logic one to a logic zero is referred to as a falling edge.
Although digital signals have a higher signal-to-noise ratio than analog signals, it is nevertheless possible for erroneous evaluation of the signal content to occur as a result of superposed noise, voltage dips caused by coupling, or settling processes after the edges.
Circuits are known which do not consider a following signal component for a certain period of time after the occurrence of a rising edge. Interference that occurs in that period of time and has a level similar to that of the signal is not evaluated as a useful signal.
In that case, the period of time is shorter than the period of time between two successive rising edges of a signal without any interference. It must be as short as required by the maximum clock rate.
A disadvantage of those circuits is the fact that the period of time in which the signal component remains unconsidered is constant and must be dimensioned in such a way that a useful signal is reliably identified even at high clock rates, that is to say short time intervals between two edges. That means, however, that when the clock rate is less than the maximum clock rate, that period of time is significantly shorter than the time interval between two edges. The insusceptibility to interference is thus greatly dependent on the clock rate. It is greatest at the maximum clock rate.
It is accordingly an object of the invention to provide a method for processing digital signals and a circuit configuration for carrying out the method, which overcome the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type and which provide a high, constant protection against interference signals at different clock rates of the digital signal.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for processing a digital input signal, which comprises assuming a first state of an activation signal upon an occurrence of a first edge of an input signal, and maintaining the first state at least for a predetermined holding time; assuming a second state of the activation signal differing from the first state after a delay of a predetermined delay time, upon an occurrence of a second edge of the input signal occurring after the holding time and differing from the first edge; and deriving a digital output signal from the input signal only when the activation signal is in the second state.
In accordance with another mode of the invention, there is provided a method which comprises selecting the first edge of the input signal as a rising edge.
In accordance with a further mode of the invention, there is provided a method which comprises selecting the input signal as a periodic clock signal.
In accordance with an added mode of the invention, there is provided a method which comprises setting a time duration of a logic state of the output signal to be shorter than a time duration between the first and second edges of the input signal.
In accordance with an additional mode of the invention, there is provided a method which comprises setting the time duration of the logic state of the output signal to be constant.
With the objects of the invention in view there is also provided a circuit configuration for processing a digital input signal, comprising an activation circuit having an input side for receiving an input signal and an output side for supplying an activation signal, the activation circuit immediately changing an instantaneous state of the activation signal in the event of a rising edge of the input signal, then maintaining the instantaneous state at least for a duration of a holding time, and changing the instantaneous state in the event of a falling edge after a delay by a delay time; and an output circuit having a first input for receiving the input signal, a second input for receiving the activation signal and an output, the output circuit forwarding the input signal to the output only in the event of a specific state of the activation signal.
In accordance with another feature of the invention, there is provided a pulse generator connected downstream of the output circuit.
In accordance with a further feature of the invention, the activation circuit includes a delay device having a non-inverting output, an inverting output and an input; a first NAND gate having an output connected to the input of the delay device, one input forming an input of the activation circuit and a further input; a second NAND gate having one input connected to the input of the delay device, a further input connected to the inverting output of the delay device and an output connected to the further input of the first NAND gate; and a NOR gate having one input connected to the input of the delay device, a further input connected to the non-inverting output of the delay device and an output forming an output of the activation circuit.
In accordance with an added feature of the invention, the output circuit includes an inverter having transistors with complementary circuitry, an input for receiving the digital input signal and an output; one transistor having a channel side connected between the output of the inverter and a reference potential, the one transistor having a gate for receiving the activation signal; and another transistor of a different conduction type from the one transistor, the other transistor connected between another reference potential and one of the transistors of the inverter, the other transistor having a gate for receiving the activation signal.
In accordance with an additional feature of the invention, the pulse generator includes a delay circuit, and a NAND gate having one input receiving the output signal directly and another input receiving the output signal time-delayed by the delay circuit.
In accordance with a concomitant feature of the invention, the delay device and/or the delay circuit has a series circuit of inverters.
The method according to the invention is suitable for digital signals in which only one edge, for example the rising edge, is used for evaluation.
The method according to the invention has the advantage of ensuring that the interference immunity does not depend on the clock rate of the digital signal. Moreover, it can be used both for periodic and for non-periodic digital signals.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a circuit configuration for processing digital signals, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.